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Careers |
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| Job Opportunity |
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Opening of Alchip Taiwan |
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|  Sr.
Engineer of QRA
| Responsibilities: |
1. ESD planning and testing.
2. Latch-up planning and testing
3. Package reliability evaluation and testing.
4. Failure analysis of reliability failure IC.
5. On-going reliability setup.
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Requirement:
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1. MS in EE/Material/Chemistry.
2. At least 5years semiconductor or design house
experience.
3. At least 3 years reliability engineering experience
and failure analysis related experience.
4. Experience in installing and ramping up new
technologies is preferred.
5. ISO-9000, QS-9000, TS-16949 related experience.
6. Fluent English communication.
7. ESD, ISO, and related certification is strongly
preferred.
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Engineer of ERP
| Responsibilities: |
The ERP Application engineer
is responsible for implementation and maintenance
ERP system, and also need to do system problem solving
and customization to fulfill user’s requirement.
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| Requirement: |
1. Bachelors Degree / Equivalent
Experience.
2. 2+ years experience in ERP system implementation
and maintenance.
3. System analysis and develop skills.
4. Experience in Oracle ERP Finance Modules is
a plus.
5. Knowledge in Oracle Database Administrator
skill is a plus.
6. Oracle ERP D2K development skill is a plus.
7. Good coordination and communication skills.
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Component Engineer |
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| Responsibilities: |
1. Process and device
optimization.
2. Product yield management.
3. Product yield improvement.
4. Failure analysis.
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Requirement:
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1. Bachelor/Master.
2. At least 1 year.
3. CMOS device, IC process, testing, FA.
4. Have experience in IC process/device/product/test
field.
5. Fluent in English.
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Product Engineer
| Responsibilities: |
1. Coordinate DE/EevE/TE/APE/RA
to do yield analysis and improvement.
2. Be in charge of handling production abnormality
and do FA/RCA/CA and implementation during MP stage.
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| Requirement: |
1. Have experience in digital
IC process/device /product/test field.
2. Knowledge of cmos device, process or IC testing.
3. Fluent in English or Japanese.
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Senior Testing Engineer
| Responsibilities: |
Testing SW/HW development. Work with
customers and team members to setup test environment
to make products delivered smoothly. Understand
need of customer and hold necessary conference calls/meetings
to track the testing schedule.
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Requirement:
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1. BS or above, major in Electronic
/ Electronic Engineer.
2. RF testing program development & debugging
over 4 years.
3. Tooling design plan.
4. RF testing know how.
5. RF tooling design know how.
6. Prefer to have the following tester experience
for LTX/CX or Verigy 84K or Teradyne iFLEX or
Credence ASL3000.
7. Prefer good communication of English.
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Staff/Sr. Engineer of Technical IP Marketing |
| Responsibilities: |
1. Provide silicon IP
/ soft IP / frond-end support to customers.
2. Perform brief assessment on both soft and hard
IP to qualify IP vendors.
3. Work with engineering departments and external
partners to prepare technical presentations for
sales. In other words, provide sales force with
compelling reasons why the customer should choose
our solutions.
4. Understand Analog and Industrial standard IP
such as ADC/DAC, PLL, LVDS, SSCG, USB, HDMI. H.264,
DDR2 Memory controller. Familiar with technology,
competition trends and various applications in wireless,
digital consumer electronics, multimedia, networking
etc.
5. Familiar with “platform solutions”（e.g., ARM/MIPS/DSP）based
on target customer needs, competitive situation,
partners’ offering and market/technology trends.
6. Monitor IP pricing and contract negotiation.
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Requirement:
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MSEE preferred.
2. At lease 3~5 years industrial experience in
system design, Silicon IP, or SoC design areas.
3. Silicon IP on multimedia, wireless experience
preferred.
4. Experience/knowledge about IP solutions which
include high speed circuits, analog circuits,
memories, and various cores-CPU/DSP/MPEG etc.
5. Good understanding of overall semiconductor
industry, trends and applications.
6. Strategic and analytical skills and team player.
7. Strong project management skills.
8. Ability to work both in a team environment
and independently.
9. Candidates will be evaluated based on their
technical competence, communication skills, analytical
skills, sense of responsibility and execution
ability.
11. Good English communication in speaking and
writing is required.
12. Communication abilities including conveyance
of ideas, ability to present are essential.
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SoC Design Engineer |
| Responsibilitie: |
Develop SoC design with
strong backend in STA, EM/IR drop electrical analysis,
and timing closure flow.
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Requirement:
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1. BS / MS degree or above with
E.E / C.S major.
2. Familiar with physical synthesis, STA analysis,
IR/EM, DFT and EDA tools.
3. Excellent skills in Verilog coding, Perl/TCL
programming is a plus.
4. Good English in both written and spoken.
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Sr. Analog / Mixed Signal IC Designer |
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| Responsibilities: |
Develop mixed signal
and analog IP for SoC design with SPICE simulation,
DRC, LVS flow, and familiar with device and process
features.
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Requirement:
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1. MSEE or BSEE with 3+ years
experience in analog and mixed signal circuit
design.
2. Familiar with Cadence design environment, HSPICE
/ HSIM simulation tools.
3. Supervise layout engineers.
4. Experience in ADC / DAC, PLL or high speed
interface（e.g. LVDS）design is a plus.
5. Knowledge of advanced process technology（90nm
and below）is a plus.
6. Good command of English.
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Staff Analog / Mixed Signal IC Designer |
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| Responsibilities: |
Develop mixed signal
and analog IP (especially in data converter) for
SoC design from specification definition, circuit
design to test, and familiar with device and process
features.
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Requirement:
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1. MSEE or above with 7+ years
experience in analog and mixed signal circuit
design.
2. Must have extensive experience in ADC / DAC
design.
3. Familiar with Cadence design environment, SPECTRE/HSPICE
simulation tools.
4. Knowledge of advanced process technology（90nm
and below）is a plus.
5. Good command of English.
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Sr. Staff Analog / Mixed Signal IC Designer |
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| Responsibilities: |
Lead a small team to
develop mixed signal and analog IP (especially in
data converter) for SoC design from specification
definition, circuit design to test, and familiar
with device and process features.
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Requirement:
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1. MSEE or above with 8+ years
experience in analog and mixed signal circuit
design.
2. Must have extensive experience in ADC / DAC
design.
3. Must have experience in leading a small design
team.
4. Familiar with Cadence design environment, SPECTRE/HSPICE
simulation tools.
5. Knowledge of advanced process technology（90nm
and below）is a plus.
6. Good command of English.
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