SoC Design Solutions
Alchip creates unique and correct-by-construction SoC design solutions enabling its customers to reduce their costs, increase product performance, decrease power consumption, and minimize die size.
Alchip excels in advanced process power management, anticipating and addressing both static and dynamic power management needs. Our unique clocking architecture and timing methodology effectively reduce overall capacitance to achieve up to 30% dynamic power savings.
We also support gated-clock designs and perform effective partitioning of multi-supply voltage designs to further reduce dynamic power usage. We have established complete design methodology to support the emerging ultra low power process nodes and offer the flexibility to re-characterize IP for ultra low voltage usage.
Unique Low Power Techniques
Alchip’s integrated design methodology adopts an accurate timing model and a precise clock design approach to avoid over-design. We provide guidance on RTL modification based on initial place and route results.
We also customize cells to close timing on critical paths and run system level noise simulation for high-speed IOs to ensure working silicon on both the chip and board levels.
Alchip's advanced design solutions save re-spin costs and optimize chip yield and die size. We achieve optimal silicon results and eliminate over-design with our proprietary clocking methodology, silicon accurate timing model, and advanced routing strategies.
Alchip's solution is production proven in over 200+ SoC chips. Our advanced solution decreases die size up to 20% and increases yield of up to 20%. We also offer advanced technology migration services to smaller geometry process nodes, decreasing die sizes by as much as 50% and allowing our customers to enjoy tremendous cost benefits for high-volume products.