Design for testability (DFT) refers to a methodology and techniques to add on-chip hardware to detect faults and manufacturing defects of a device under test. These techniques are also used for chip diagnostic, device characterization and failure analysis.  DFT design consists of tests for random logic, IP, memory elements, and IO. The design requires a detailed planning and knowledge on how to minimize the impact on normal function performance and additional area overhead introduced by the DFT logic, and also on how to maximize the fault coverage in order to detect as many faults as possible.  By adopting this technique, test pattern generation and chip testing could be done in a more efficient and effective way to filter out defect parts such that the testing cost could be reduced and chip production yield could also be greatly improved.