Test & Assembly
Alchip realizes that being your Trusted Silicon Partner is more than simple production. We stand behind our customers with total solutions so you can rest assured that your SoC needs are met. Alchip's testing support tests all silicon solutions of all kinds, from low-cost to high-end SoCs, and these cost effective SW/HW solutions are optimized to the characterization, specs. An in-house high-end SOC tester (Alchip in-house Advantest V93K) provides fast TAT sample delivery and characterization.
Additionally, we offer multiple testing sites (in parallel) for cost-down testing in the MP stage. To increase efficiency in this area, Alchip skips redundant testing items, including wafer sorting, speeds up test frequency and smartly prioritizes chip-test based on cost to save our customers' cost. Providing both high-quality testing capabilities and a complete EDA environment, Alchip is prepared to meet our customers' product-roadmap requirements.
Alchip's software and hardware (SW/HW) development flow is a five-step process to ensure you only receive the highest quality of products. The first is the choice of best fitted tester which has a cost benefit; Alchip has much experience of performing this task for Advantest, Teradyne, and Credence. The second step is to make the specific test tooling which helps reduce guess work of trial and error. Alchip has experience manufacturing these tools for wafers (probe card) and packaging (load board, sockets, change kits) scenarios.
The third step is the pattern conversion. Having timing advantages, Alchip can achieve success of over 500 pattern files from VCD/WGL to tester format. Next, program development and debugging begins, which again offers timing benefits, and has been used in high-speed (LVDS, SATA, DDR2, USB, V-by-one), analog (ADC, DAC), DFT (Scan, BIST, JTAG). Finally, we test our SoC's characterization, for which we are experts at, with Shmoo/Pin margin tools, timing margin analysis, and power/IO level tests.
Testing Engineering Capabilities & Testing SW/HW Development Flow
Testing SW/HW Development Capabilities
Alchip provides a broad range of test solutions to minimize test costs and to provide compatible test solutions consistent with the customers test environment.
Alchip offers our customers state-of-the-art, deliverable SoC packaging with support from world leading technologies. We are a worldwide front runner in Flip Chip technology and chip-on-chip technology and we have the lowest cost for wire bond chip stacking. Additionally, by leveraging long term, strategic partnerships, Alchip offers a cost effective facility which meets our customers' demands and we are able to deliver DDR DRAM. Our packaging solutions include: SiP, MCM, MCP, WLCSP, Flip Chip, CoC, PiP, PoP and more scenarios.
Alchip's SoC Solution Benefits
Alchip offers our customers in-house substrate design capabilities ᾿including: pre-design (co-design with IC floor plan and package ball map constraint) and post-design (the same flow/procedure/design rule as assembly house). Our customers enjoy high IO density package with low costs via our optimized package/substrate utilization and pre-design before IDR to achieve a balance between performance and cost/schedule. Lastly, our hands-on experience with high-end packaging and SMT processes helps to produce a low cost solution before FDR, during the design stage.
Result for Wire Bond Type:
Feasibility study for wire layout and finger/P&G ring layout
Substrate structure (Signal/P/G layer definition) / trace width/space and estimate for substrate
Result for Flip Chip Type:
Feasibility study for bump pitch and bump layout
Substrate structure (Signal/P/G layer definition) /trace width/space and estimate for substrate electric/thermal