CoWoS
About CoWoS
CoWoS (Chip on Wafer on Substrate) is a high-density packaging technology for high-performance chips. The architecture was developed by TSMC in 2012.
- An intermediate layer, called a silicon interposer, is placed on the package board.
- Multiple silicon dies are placed closely together on a silicon interposer.
- Micro bumps connect the silicon die to the silicon interposer.
- Through-silicon via (TSVs) connect the silicon interposer’s front and back surfaces.
- Bumps connect the back side of the silicon interposer to the package board.
This configuration improves performance by reducing the wire length of the silicon die interconnects.
CoWoS Design Services
Alchip’s CoWoS design services provide comprehensive services such as system planning, physical implementation, DFT, logic verification, and warpage simulation.
System Planning
- System architecture plan
- System power supply planning
- Package ball assignments
- Interposer die placement
- SoC floorplan and IP/IO placement collaboration
Physical Design
- SoC integration collaboration
- Interposer physical design
- Package substrate design
- HBM hardening and integration collaboration
DFT Logic
- Test plan collaboration
- IP test logic collaboration
Logic Verification
- SoC vs. interposer connection verification
- Interposer vs. package connection verification
- Power supply planning and connectivity
Mechanical and Warpage Simulation
- CoW warpage simulation to meet TSMC CoWoS production process control
- Package warpage simulation to meet SMT yield and board level RA
CoWoS Production
- Testing and Yield Improvement
- SoC CP1 testing for KGD (Known-good die)
- Interposer/CoW PGD (partial known die) testing
- Final test and yield improvement
- Characterization & Qualification/ORM
- Device qualification
- Package qualification
- Production Management
- Logistic control: HBM2E/Cap/Lid/SBS
- RMA and FA Handling
APLink: Alchip’s original D2D (Die-to-Die) IP
- 5nm APLink 3.0 has taped out.
Click here for details >>
Alchip provides complete CoWoS 2.5D homogeneous and heterogeneous integration services.
We support major HBM2/HBM2E, PHY/controllers and D2D venders.
We’ve completed the development of a commercial HBM2 project with many more in various stages of development.
About CoWoS
CoWoS (Chip on Wafer on Substrate) is a high-density packaging technology for high-performance chips. The architecture was developed by TSMC in 2012.
- An intermediate layer, called a silicon interposer, is placed on the package board.
- Multiple silicon dies are placed closely together on a silicon interposer.
- Micro bumps connect the silicon die to the silicon interposer.
- Through-silicon via (TSVs) connect the silicon interposer’s front and back surfaces.
- Bumps connect the back side of the silicon interposer to the package board.
This configuration improves performance by reducing the wire length of the silicon die interconnects.
CoWoS Design Services
Alchip’s CoWoS design services provide comprehensive services such as system planning, physical implementation, DFT, logic verification, and warpage simulation.
System Planning
- System architecture plan
- System power supply planning
- Package ball assignments
- Interposer die placement
- SoC floorplan and IP/IO placement collaboration
Physical Design
- SoC integration collaboration
- Interposer physical design
- Package substrate design
- HBM hardening and integration collaboration
DFT Logic
- Test plan collaboration
- IP test logic collaboration
Logic Verification
- SoC vs. interposer connection verification
- Interposer vs. package connection verification
- Power supply planning and connectivity
Mechanical and Warpage Simulation
- CoW warpage simulation to meet TSMC CoWoS production process control
- Package warpage simulation to meet SMT yield and board level RA
CoWoS Production
- Testing and Yield Improvement
- SoC CP1 testing for KGD (Known-good die)
- Interposer/CoW PGD (partial known die) testing
- Final test and yield improvement
- Characterization & Qualification/ORM
- Device qualification
- Package qualification
- Production Management
- Logistic control: HBM2E/Cap/Lid/SBS
- RMA and FA Handling
APLink: Alchip’s original D2D (Die-to-Die) IP
- 5nm APLink 3.0 has taped out.
Click here for details >>
Alchip provides complete CoWoS 2.5D homogeneous and heterogeneous integration services.
We support major HBM2/HBM2E, PHY/controllers and D2D venders.
We’ve completed the development of a commercial HBM2 project with many more in various stages of development.
