Alchip regularly notifies a quality policy to all employees. Employees are engaged in providing the highest quality and the latest knowledge and skills, and are committed to continuous quality improvement so that we can achieve the highest satisfaction for our customers.
Alchip regularly notifies a quality policy to all employees. Employees are engaged in providing the highest quality and the latest knowledge and skills, and are committed to continuous quality improvement so that we can achieve the highest satisfaction for our customers.
Quality system and document management
ISO compliance, quality-related training, quality system improvement and ISO-related document management.
Quality assurance
As a fabless company that outsources all manufacturing activities, Alchip is building a quality control assurance system in cooperation with our suppliers.
A quality assurance team is responsible for evaluating new suppliers and managing supplier quality assurance and changes.
Quality system and document management
ISO compliance, quality-related training, quality system improvement and ISO-related document management.
Quality assurance
As a fabless company that outsources all manufacturing activities, Alchip is building a quality control assurance system in cooperation with our suppliers.
A quality assurance team is responsible for evaluating new suppliers and managing supplier quality assurance and changes.
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Certification |
ISO9001 |
ISO/ |
ISO14001 |
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ALCHIP | |||
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Wafer | |||
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Assenbly | |||
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Test |
Reliability assurance
We design, execute and certify reliability tests suitable for each product.
The table below is an example of a reliability test performed when a new product is certified.
The reliability test is an accelerated test to confirm the lifetime of devices and packages, and to detect potential failures by deteriorating over a short period of time.
◊ Reliability test items ◊
Pre-condition (pre-con.)
Pre-Condition
To simulate the environment conditions of the SMT process. Pop-corn, poor solderability, can be found on failed parts.Improper molding material & process may induce this failure.
High Temperture Operation Life Test (HTOL)
HTOL (High Temperature Operation Life-time Test)
Using temperature and voltage to stress ICs to determine operation lifetime of ICs due to foundry process, & to evaluate lifetimes of ICs.
High Temperture Storage Life Test (HTST)
HTST (High Temperature Storage Test)
To detect the effect of time and temperature under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.
Highly Accelerated Stress Test (u-HAST)
HAST (Highly Accelerated temperature & humidity Stress Test)
To verify the capability of packages to prevent the moisture penetration. This moisture penetration will make the metallization, PAD, wire corrosion and malfunction.
Temperature cycling Test (TCT)
TCT (Temperature Cycle Test)
To enhance the mechanical stress induced by different thermal expansion coefficient of the materials. Delamination, package crack, can be found on failed samples. Poor molding process, lead frame integrity & die attach process may induce this failure.
Human Body Model Test (ESD-HBM)
Human Body Model Test (ESD-HBM)
This model (HBM) simulates ESD （Electrostatic discharge) caused by a discharge from a human that is easily charged, to a device. For HBM testing, normal failure modes would be gate oxide, contact, and/or junction damage. To simulate a discharge from human body, 100 pF capacitor and a 1.5K ohm resistor are specified in the model.
Charged Device Model Test (ESD-CDM)
Charged Device Model Test (ESD-CDM)
When a device itself has an electrostatic charge and contacts to a grounded conductor via a package terminal (pin, ball etc.), a discharge will occur from the device to the outside ground, and it may cause the critical damage to the device.
This type of ESD could be simulated by CDM.
Currents due to CDM are higher than HBM currents because of smaller resistance in the discharging path.
Latch-Up (LU)
Latch-up
To verify the circuit resistance to latch-up. Latch-up is also an intrinsic characteristic of a chip, & depends on the devices arrangement of circuit. It is important to reduce the EOS (electrical over stress) failure due to latch-up.
*Complies with JEDEC
Reliability assurance
We design, execute and certify reliability tests suitable for each product.
The table below is an example of a reliability test performed when a new product is certified.
The reliability test is an accelerated test to confirm the lifetime of devices and packages, and to detect potential failures by deteriorating over a short period of time.
◊ Reliability test items ◊
Pre-condition (pre-con.)
Pre-Condition
To simulate the environment conditions of the SMT process. Pop-corn, poor solderability, can be found on failed parts.Improper molding material & process may induce this failure.
High Temperture Operation Life Test (HTOL)
HTOL (High Temperature Operation Life-time Test)
Using temperature and voltage to stress ICs to determine operation lifetime of ICs due to foundry process, & to evaluate lifetimes of ICs.
High Temperture Storage Life Test (HTST)
HTST (High Temperature Storage Test)
To detect the effect of time and temperature under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.
Highly Accelerated Stress Test (u-HAST)
HAST (Highly Accelerated temperature & humidity Stress Test)
To verify the capability of packages to prevent the moisture penetration. This moisture penetration will make the metallization, PAD, wire corrosion and malfunction.
Temperature cycling Test (TCT)
TCT (Temperature Cycle Test)
To enhance the mechanical stress induced by different thermal expansion coefficient of the materials. Delamination, package crack, can be found on failed samples. Poor molding process, lead frame integrity & die attach process may induce this failure.
Human Body Model Test (ESD-HBM)
Human Body Model Test (ESD-HBM)
This model (HBM) simulates ESD （Electrostatic discharge) caused by a discharge from a human that is easily charged, to a device. For HBM testing, normal failure modes would be gate oxide, contact, and/or junction damage. To simulate a discharge from human body, 100 pF capacitor and a 1.5K ohm resistor are specified in the model.
Charged Device Model Test (ESD-CDM)
Charged Device Model Test (ESD-CDM)
When a device itself has an electrostatic charge and contacts to a grounded conductor via a package terminal (pin, ball etc.), a discharge will occur from the device to the outside ground, and it may cause the critical damage to the device.
This type of ESD could be simulated by CDM.
Currents due to CDM are higher than HBM currents because of smaller resistance in the discharging path.
Latch-Up (LU)
Latch-up
To verify the circuit resistance to latch-up. Latch-up is also an intrinsic characteristic of a chip, & depends on the devices arrangement of circuit. It is important to reduce the EOS (electrical over stress) failure due to latch-up.
*Complies with JEDEC
