Alchip realizes that being your Trusted Silicon Partner is more than simple production, it takes tested quality which we ourselves stand behind so you can rest assured your SoC needs are met. Alchip's testing support tests all silicon solutions of all kinds, from low-cost to high-end SoCs, and these cost effective SW/HW solutions are optimized to the characterization, specs. An in-house high-end SOC tester (Alchip Hsinchu office's Verigy 93K) provides fast TAT sample deliver and characterization.
Additionally, we offer multiple testing sites (in parallel) for cost-down testing in the MP stage. To increase efficiency in this area, Alchip skips redundant testing items, including wafer sorting, speeds up test frequency and smartly prioritizes chip-test based on cost to save our customers' money. Providing both high-quality testing capabilities and a necessary EDA environment, Alchip is prepared to meet our customers' product-roadmap requirements.
Alchip's software and hardware (SW/HW) development flow is a five step process to ensure you only receive the highest quality of products. The first is the choice fit tester which has a cost benefit; Alchip has experience performing this test for Verigy, Teradyne, Credence, and Advantest. The second step is tooling manufacturing which helps to reduce guess work of trial and error. Alchip has experience manufacturing these tools for wafers (probe card) and packaging (load board, sockets, change kits) scenarios.
The third step is pattern conversion. Having timing advantages, Alchip can achieve success of over 500 pattern files from VCD/WGL to tester format. Next, program development and debugging begins, which again offers timing benefits, and has been used in high-speed (LVDS, SATA, DDR2, USB), analog (ADC, DAC), DFT (Scan, BIST, JTAG), and CMOS image sensor and memory tests. Finally, we test our SoC's characterization, for which we are experts at, with Shmoo/Pin margin tools, timing margin analysis, and power/IO level tests. |
Alchip offers our customers state-of-the-art, deliverable SoC packaging with support from world leading technologies. We are a worldwide front runner in Flip Chip technology and chip-on-chip technology and we have the lowest cost for wire bond chip stacking. Additionally, by leveraging long term, strategic partnerships, Alchip offers a cost effective facility which meets our customers' demands and we are able to deliver DDR DRAM. Our packaging solutions include: SiP, MCM, MCP, WLCSP, Flip Chip, CoC, PiP, PoP and more scenarios. |
