IP Subsystem Service

IP Subsystem Service

It’s increasingly common practice for complex SoC’s to procure and implement standard-based, proven, general-purpose design assets, such as IP from trusted third parties. At Alchip, our best-in-class IP platform meets all of your requirements. We have a strong, symbiotic relationships with all of our IP partners

It’s increasingly common practice for complex SoC’s to procure and implement standard-based, proven, general-purpose design assets, such as IP from trusted third parties. At Alchip, our best-in-class IP platform meets all of your requirements. We have a strong, symbiotic relationships with all of our IP partners

IP Subsystem Design

Today, companies want to minimize design resources and are focusing on user function blocks to shorten the design cycle. All IP in the Alchip portfolio are provided with configuration settings to optimize each design.

There’s also increased demand to isolate part of the SoC as a system, connecting and verifying IP, and improving performance.

Regardless of the need, Alchip provides a wide range of IP sub-system design services to meet just about every design need:

  • IP configuration, integration, subsystem design, verification service
  • FPGA prototype, emulation
  • Soft wafer driver porting
  • Chip bring-up

Interface IP Subsystem Integration

Integration

  • Subsystem RTL Design
    • Controller/PHY connection
    • Clock/Reset gen
    • SRAM replacement
  • Front-end Flow
    • LINT/SDC/CDC check
    • SDC migration
    • Synthesis
    • Formal check
    • STA timing analysis

Verification

  • IP level simulation
  • Subsystem level simulation
  • SoC level simulation
  • Pre and post-Netlist simulation

ES Bring up and Debug

Here’s an example of an interface IP sub-system design. Our experienced Front-End Design Team provides your choice of all, or just some of these design and verification services.

IP Subsystem Design

Today, companies want to minimize design resources and are focusing on user function blocks to shorten the design cycle. All IP in the Alchip portfolio are provided with configuration settings to optimize each design.

There’s also increased demand to isolate part of the SoC as a system, connecting and verifying IP, and improving performance.

Regardless of the need, Alchip provides a wide range of IP sub-system design services to meet just about every design need:

  • IP configuration, integration, subsystem design, verification service
  • FPGA prototype, emulation
  • Soft wafer driver porting
  • Chip bring-up

Interface IP Subsystem Integration

Integration

  • Subsystem RTL Design
    • Controller/PHY connection
    • Clock/Reset gen
    • SRAM replacement
  • Front-end Flow
    • LINT/SDC/CDC check
    • SDC migration
    • Synthesis
    • Formal check
    • STA timing analysis

Verification

  • IP level simulation
  • Subsystem level simulation
  • SoC level simulation
  • Pre and post-Netlist simulation

ES Bring up and Debug

Here’s an example of an interface IP sub-system design. Our experienced Front-End Design Team provides your choice of all, or just some of these design and verification services.